ANALYSIS OF DELAY LOCKED LOOP USED IN DRAM INTERFACE FOR HIGH SPEED IN MHz RANGE OF FREQUENCY

The proposed architecture is an all-digital delayand phase-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in analog DLL/PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit ability of DLLs and PLLs to provide fixed timing relationships lets component manufacturers and system integrators relax the specifications. This analysis starts with an explanation of technology trends regarding DLL for DRAM and describes important DLL specifications and design approaches necessary for DLL use in DRAM: lock time, lock range, lock cycles, DQSCK (DQS rising edge output access time from the rising edge of CK), and wake-up time from power down modes. In this paper presents the application feasibility of mixed mode PLL-DLL in DRAM. Jitter analysis of mixed mode PLL-DLL in DRAM environment has been carried out. According to the jitter type, this model can be used as pure. PLL or pure DLL or a mixed PLLDLL. It is observed that mixed mode PLL-DLL architecture can combine the advantage from both PLL and DLL to reduce jitter in DRAM.